1. Field of the Invention
The invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with mini SONOS cells.
2. Description of the Prior Art
With increasing shrinkage of semiconductor devices, the integration degree is doubled every three years according to a scaling rule, and speed of semiconductor devices is increasing and power consumption thereof is decreasing. The production of finer MOS type FETs has been being accomplished by decreasing a dimension of a gate electrode, decreasing a thickness of a gate insulating layer and highly accurately controlling an impurity concentration profile in a channel forming region or in its vicinity. And, driving capability of semiconductor devices is improved and a parasitic capacitance thereof is decreased according to finer semiconductor devices. In general, in circuits having a CMOS structure, an operating rate is determined depending upon a rate of charging (or discharging) for giving an output of a logic gate at a certain stage to drive a capacitive load in a subsequent logic gate. Therefore, the operating rate is in proportion to the inverse number of capacity of the capacitive load and to the driving capability.
For accomplishing the formation of finer semiconductor devices, conventionally, there has been employed a logic gate structure adjacent to the MOS structure, i.e., a structure having a logic gate composed of a gate oxide layer and polysilicon gate electrode layer is disposed on a semiconductor substrate while the edges of the logic gate is sitting on a portion of two adjacent shallow trench isolations (STIs), in which a depletion region is created directly under the logic gate and between the two STIs. In this structure, as at least a portion of the STI is overlapped by the gate oxide layer of the logic gate, an inevitable edge fringing capacitance is created at the overlapped region, which in most circumstances, would induce an inverse narrow width effect.